The present invention relates to a semiconductor storage device that is electrically erasable and programmable and has non-volatility.
For achieving low power consumption and compacting of electronic equipment, there is needed a semiconductor storage device (EEPROM) that has a high degree of integration and a low power consumption and is electrically erasable and programmable. The semiconductor storage device having the non-volatility has a floating gate between its channel region and gate electrode, and this floating gate is operated as a carrier confining region, the device generally having the following problems.
(i) Since the number of injection and removal of electric charges in the floating gate are limited due to the problem of a reduction in reliability resulting from a hot carrier, there is a limitation in the number of times of write and erase operations.
(ii) A relatively thick insulating film is needed for maintaining the non-volatility. In order to inject an electron or a positive hole into the floating gate by the FOWLER-NORDHEIM tunnel effect through this thick insulating film, a high voltage of not lower than 10 V is required in the present situation. As a result, a hot carrier is generated, and this causes a deterioration of the insulating film by the influence of the formation of a trap and a reaction in the interface due to the hot carrier and alleviation of the hot carrier.
(iii) Since the write and erase operations are executed by a very small current flowing by charging and discharging of the floating gate, the time of charging and discharging is long (on the millisecond order).
Accordingly, a semiconductor storage device that resolves the above problems (i) through (iii) is proposed (Japanese Patent Laid-Open Publication No. HEI 7-302848). In this semiconductor storage device, as shown in FIG. 5, a source region 108 and a drain region 110 are formed at a specified interval on a semiconductor substrate 120, and a floating gate 104 is formed in a region opposite to a channel region 106 between the source and drain regions 108 and 110 via an insulating layer 112 on the semiconductor substrate 120. Then, the floating gate 104 is covered with an insulating layer 102, and a control gate 100 is formed on the insulating layer 102. As shown in FIG. 6, the floating gate 104 is provided in the form of a cluster or an island 122 constructed of a semiconductor material having a diameter of 1 nm to 20 nm. Then, the insulating layer 112 located between the channel region 106 and the floating gate 104 is made as thin as possible so as to allow an electron to directly pass through the layer 112 by the tunnel effect, and the energy level of the floating gate 104 is made lower than that of the channel region 106, thereby preventing the trapped electron from easily escaping.
The following two reference documents describe the fabricating methods of the above floating gate.
(1) A silicon nanocrystals based memory, Sandip Tiwari et al., Appl. Phys. Lett. 68 (10), p1377 (1996) PA0 (2) Fast and Long Retention-time Nano-Crystal Memory, Hussein I. Hanafi et al., IEEE Trans. Electron Device, Vol. 43, p1553 (1996)
FIG. 7 shows a schematic diagram of a cross-section of a semiconductor storage device having a floating gate described in the above literature, where a tunnel insulating film 202 having a thickness of 1.1 nm to 1.8 nm is formed on a semiconductor substrate 201 on which a source region 206 and a drain region 207 are formed, and nano-crystals 203 having a diameter of 5 nm are formed at intervals of 5 nm on the tunnel insulating film 202 by a CVD (Chemical Vapor Deposition) system. The density of the nanocrystal 203 is 1.times.10.sup.12 cm.sup.-2. Further, a control gate insulating film 204 is formed on the nanocrystals 203, and SiO.sub.2 is deposited to a thickness of 7 nm on the control gate insulating film 204, thereby forming a control gate 205.
FIGS. 8A through 8C show a fabricating method of a semiconductor storage device having a floating gate described in the above literature, according to which a thermal oxide film 302 is formed to a thickness of 5 nm to 20 nm on a semiconductor substrate 301 (shown in FIG. 8A) and a high dose of ions of silicon Si or germanium Ge is implanted into the thermal oxide film 302 in a supersaturated state (shown in FIG. 8B). The ion implantation in this case is performed under, for example, the conditions of 5 keV and 5.times.10.sup.15 cm.sup.-2. Subsequently, a heat treatment is effected for 30 minutes at a temperature of 950.degree. C. in an atmosphere of nitrogen N.sub.2, thereby growing nano-crystals 303 of silicon Si or germanium Ge having a diameter of 5 nm in the thermal oxide film 302. Then, a source region 305 and a drain region 306 are formed at a regular interval on the semiconductor substrate 301, and a gate electrode 304 is formed on the thermal oxide film 302 oppositely to a region located between the source region 305 and the drain region 306 (shown in FIG. 8C).
As described in the above literatures (1) and (2), a shift voltage .DELTA.Vth of a threshold voltage Vth when one electron is stored in one nano-crystal is expressed by the following equation: EQU .DELTA.Vth=q(n.sub.wel /.epsilon..sub.ox)(t.sub.cnt1 +(.epsilon..sub.OX /.epsilon..sub.si)t.sub.well /2) (equation 1)
where
q: electron charge, PA1 n.sub.well : nano-crystal density, PA1 .epsilon..sub.ox : dielectric constant of oxide film, PA1 t.sub.cnt1 : film thickness of control gate oxide film, PA1 .epsilon..sub.si : dielectric constant of silicon, and PA1 t.sub.well : nano-crystal size. PA1 the floating gate region being comprised of a plurality of granular regions discretely linearly arranged substantially parallel to a surface of the channel region or a linear region continuously formed substantially parallel to the surface of the channel region. PA1 the floating gate region being comprised of a plurality of nano-crystals linearly arranged substantially parallel to a surface of a channel region.
As is apparent from the above equation 1, it can be understood that a variation in device characteristics (.DELTA.Vth) can be reduced by reducing a variation in nano-crystal density n.sub.well and nano-crystal size t.sub.well. The film thickness of the tunnel insulating film located between the nano-crystal and the channel is a determinant of the direct tunneling of an electron to the nano-crystal (the probability of tunneling is expressed by a function of the film thickness of the tunnel insulating film), and therefore, a variation in the film thickness of the tunnel insulating film influences the variation in write characteristics. As described above, the above nano-crystal density, nano-crystal size and film thickness of the tunnel insulating film located between the nano-crystal and the channel are the principal parameters to be controlled inherent in the memory.